Here is just another attempts for my blog site. The last update of my github home page is 2019-11-29 16:35:55, 6 yrs ago.
After one year of my PhD study in HKUST(GZ), I found that there're just too many information or knowledge I need to follow up. Frankly speaking, I'm in the hard period of transforming my research area to LLM-related optimizations. The most obvious reason is that it is indeed the hottest research topic currently and also for next few years. Second, I found building hardware accelerators for non-LLM workload (including Graph Pattern Mining, which is my previous project) is not time-efficient and also unrealistic for real-world adoption. For Verilog/Chisel hardware design, I'm required to build another codebase of SystemC for simulation as RTL simulation is too slow for any real dataset. The hardware implementation is impossible for ASIC and too time-consuming for debugging for FPGA. HLS, in the other hand, can generate simulator and hardware with one codebase. But it suffers from heavy RTL overhead and day-long implementation time. Additionally, the baselines of hardware accelerator are hard to access and not very trustful as everyone claims a cycle-accurate simulator is used. I'm a bit tired of building hardware accelerator for only research projects. But I'm also confused for the next direction because the LLM world is ever-changing.
So I want to restart my blog site to help me organize my thoughts, ideas and even some interesting things. I also have another private Notion site for recording research plans and progress.